The resistance of a vertical power MOSFET has several components: the resistance of the channel, the resistance beyond the channel where the current is spreading out, the resistance in a relatively lightly-doped epitaxial layer which is normally a part of these devices, and the resistance of the heavily-doped substrate. In addition, vertical double-diffused (DMOS) devices with planar channels (known as planar VDMOS) have an additional component of resistance that is due to the crowding of the current between the depletion regions that surround the body regions.
FIGS. 1-11 illustrate several aspects of these resistance components. FIGS. 1 and 2 show cross-sectional views of two classes of vertical MOSFETs each of which includes an N-epitaxial (epi) layer 12 which is grown on an N+ substrate 11, which functions as the drain. FIG. 1 shows a planar DMOS 10 including P-body regions 13, P+ body contact regions 14, and N+ source regions 15. A gate 16 is formed over the top surface of the epi-layer 13 and is separated from the top surface by an oxide layer 17. The N+ source regions 15 are contacted by a metal layer 28 which also forms a short between the N+ source regions 15 and the P+ body contact regions 14 and thereby prevents the parasitic NPN bipolar transistor from turning on. As shown by the arrows, when the device is turned on current flows from the N+ source regions 15, laterally through channel regions in the P-body regions 13 and then downward through the N-epi layer 12 to the N+ substrate 11 (drain).
MOSFET 20 shown in FIG. 2 is a trench-gated MOSFET in which a gate 26 is formed in a trench and is separated from the N-epi layer 12 by an oxide layer 27. The gate trenches typically form a lattice or array of cells which in FIG. 2 includes a MOSFET cell 29 and a diode cell 30. MOSFET cell 29 includes a P-body region 23, a P+ body contact region 24, and an N+ source region 25. N+ source region 25 and P+ body contact region 24 are contacted and shorted together by a metal layer 28. As shown by the arrows, when the device is turned on currents flow from the N+ source region 25 downward through channel regions adjacent the walls of the trenches, through the N-epi layer 12 and into the N+ substrate (drain).
Diode cell 30 includes a deep P+ diffusion 31 which ensures that voltage breakdown occurs away from the trench walls. Impact ionization near the trench walls could cause hot carriers to be injected into and damage the gate oxide 27. Preferably there is a diode cell for a given number of MOSFET cells as taught in application Ser. No. 08/459,555, filed Jun. 2, 1995, which is incorporated herein by reference. Alternatively, the deep P+ diffusion could be included within the MOSFET cell 29 as taught in U.S. Pat. No. 5,072,266 to Bulucea et al.
As the carriers (electrons) drift through the N-epi layer 12 in MOSFETs 10 and 20 a voltage develops across N-epi layer 12 (sometimes referred to as a "drift" region). The magnitude of this voltage depends on the thickness of and dopant concentration in N-epi layer 12, which are normally chosen in a compromise to provide a variety of features and characteristics for the device. In particular the thickness and dopant concentration are selected to provide a particular blocking voltage when the device is turned off. Generally speaking, the lower the dopant concentration and the thicker the N-epi layer 12 (between the top interface of the N+ substrate 11 and a P-type region), the higher the blocking voltage. In FIG. 1 X.sub.epi (off) designates the vertical distance between the N+ substrate 11 and the lower boundary of P-body region 13, and in FIG. 2 X.sub.epi (off) designates the vertical distance between the N+ substrate 11 and the lower limit of deep P+ diffusion 31. In each case X.sub.epi (off) represents the thickness of N-epi layer 12 that must support the voltage across the device when it is turned off. Note also in FIGS. 1 and 2 that X.sub.jB designates the level of the lower junction of the P-body regions 13,23 relative to the surface of the epi-layer, which is labeled zero. In FIG. 1 X.sub.jB coincides with the beginning of X.sub.epi ; in FIG. 2 X.sub.epi (off) is not referenced to X.sub.jB.
The cross-sections AA' in FIG. 1 and CC' in FIG. 2 correspond to diodes which are formed at the junction of N-epi layer 121 and P-body region 13 and deep P+ diffusion 31, respectively. The cross-sections BB' and DD' designate the regions in which the current flows vertically through the N-epi layer 12.
The diodes at cross-sections AA' and CC' are represented generally by a diode 32 on the left side of FIG. 3 which shows a P or P+ region 33, an N+ region 35 and an intervening N-epi layer 34 (referred to as a PN or PIN avalanche clamp). The thickness of the N-epi layer 34 is designated X.sub.epi (net). The right side of FIG. 3 shows a graph of the strength of the electric field (E=dV/dx) in the diode 32. The electric field reaches a peak at the junction of P or P+ region 33 and N-epi layer 34 and then drops with increasing depth. If N-epi layer 34 is relatively heavily doped, the electric field (curve labeled PN) drops over a short distance; if N-epi layer 34 is lightly doped the electric field (curve labeled PIN(reachthrough)) is relatively flat indicating that the depletion region extends all the way to N+ substrate 35; if N-epi layer 34 is doped to an intermediate level the electric field (curve labeled P.nu.N(reachthrough)) the depletion region again reaches through the entire N-epi layer 34 but the electric field is not flat across the entire layer 34. Rather, in the last case the electric field slopes to some degree until it reaches the N+ region 35. Neither the P or P+ region 33 nor the N+ region 35 can support any significant electric field. Since the breakdown voltage is roughly equal to the integral of the electric field over the interval X.sub.epi (net), it is apparent that the area under the triangle or trapezoid gives a rough estimate of the voltage of the device.
Thus if the N-epi-layer 34 is made thinner or doped more heavily, the breakdown voltage is reduced. On the other hand, a thinner, more heavily doped epi layer has a lower resistance when the device is turned on. A variety of techniques have been used to optimize the device by fabricating the thinnest possible, most heavily doped epi-layer that still provides an adequate breakdown voltage. All of these variations are only a few percentage points apart in terms of what is needed to provide the optimal doping/thickness combination to meet and support the required breakdown voltage.
FIG. 4 illustrates a graph that is available from many sources showing the "reach-through" breakdown voltage of a PIN diode as a function of the "background" doping concentration of the intermediate layer (C.sub.B) for various intermediate layer thicknesses (designated as W.sub.EPI, which in this particular publication is equivalent to X.sub.epi (off) in FIGS. 1 and 2). The graph of FIG. 4 is taken from Semiconductor Technology Handbook, Technology Associates, page 8-9 (1980). If W.sub.EPI is an infinite thickness, there is a one-to-one correspondence between the background dopant concentration and the breakdown voltage. Since FIG. 4 is plotted on log-log paper, this implies a strong dependence between the dopant concentration and breakdown voltage. If the background concentration is increased two orders of magnitude from 10.sup.15 cm.sup.-3 to 10.sup.17 cm.sup.-3, for example, the breakdown voltage falls from about 300 V to about 15 V. If the intermediate layer is made thinner, then ultimately the breakdown voltage becomes independent of background concentration and varies only with the thickness of the intermediate layer. Between these extremes there is a region where the plots are curved, indicating that the breakdown voltage is a result of both the background concentration and intermediate layer thickness.
Reducing the thickness and increasing the dopant concentration of the intermediate layer improves the on-resistance of the device but, as indicated by FIG. 4, this would also reduce the device's breakdown voltage. Furthermore, in designing a MOSFET a 20-25% variation in the epi layer thickness and a 10-20% variation in the dopant concentration must be anticipated. Accordingly, to guarantee a desired breakdown voltage one must design the device to have a thicker epi layer and a lower dopant concentration. For example, according to FIG. 4, to design a 60 V device X.sub.epi (off) could be as low as about 2 .mu.m, and the dopant concentration at that thickness could be as high as about 5.times.10.sup.15 cm.sup.-3. Alternatively, the epi doping could be increased beyond 1.2.times.10.sup.16 cm.sup.-3 but the thickness would have to exceed 0.3 .mu.m to meet a 60 V breakdown specification. However, to take account of manufacturing variations E.sub.fepi (off) would have to be designed to be in the range of 2 to 4 .mu.m (i.e., 3.+-.1 .mu.m) and the dopant concentration would have to be designed to be in the range of 4.times.10.sup.5 cm.sup.-3. Such a combination represents the points of the thinnest epi (2 .mu.m) curve where the breakdown voltage does not vary substantially with doping. In this approach a 20% increase in resistivity at the thinnest (2 .mu.m) epi would just barely meet the target breakdown voltage.
FIG. 5 is a cross-section showing a portion of an N-epi layer 50 and an N+ substrate 51. The upper boundary of N-epi layer 50 is designated X.sub.jB, and the thickness of N-epi layer 50 is X.sub.epi (on). N-epi layer 50 has a dopant concentration N.sub.epi and a corresponding resistivity .rho..sub.epi. Ignoring the resistance in the region above X.sub.jB and in the N+ substrate 60, the resistance of N-epi layer 61 (which is treated as the "drain resistance" R.sub.D), is then ##EQU1##
where A is the area. Normalizing the resistance by area yields: EQU R.sub.D.multidot.A=.rho..sub.epi X.sub.epi (on)
Thus the product R.sub.D A is the quantity (the specific on-resistance) that is to be minimized. Applying the data of FIG. 4 to R.sub.D A (i.e., considering only the resistance of the N-epi layer 61) yields the graph of FIG. 6, which plots R.sub.D A as a function of the breakdown voltage BV(rated) for N-channel and P-channel devices. FIG. 6 is taken from R. K. Williams and R. Blattner "Benefits of DMOS Voltage Scaling On Synchronous Buck Regulator Efficiency", 1993 International Symposium on Semiconductor Devices, pp. 146-151. One general conclusion of that article is that the optimal solution yields a curve of E vs..times. which is similar to the trapezoidal curve P.nu.N(reachthrough) shown in FIG. 3. The optimal breakdown voltage is in the range of 20-30 V/.mu.m, depending on the dopant concentration. If the silicon is doped more heavily and is thicker than the minimum reachthrough thickness, the breakdown voltage is closer to 30 V/.mu.m; if the silicon is doped more lightly the breakdown voltage is closer to 20 V/.mu.m. FIG. 6 shows curves for R.sub.D A both with and without the substrate. As expected, the values of the coefficients in an equation for ionization rate vary with the author and the fabricated devices. Since the breakdown voltage depends on both doping and thickness, the minimum thickness and maximum doping for a given breakdown voltage decrease with doping despite the fact that the critical electrical field is increasing. The curve labelled Hu[2] in FIG. 6 illustrates the effect of these constants on the breakdown vs. concentration curve. See also, Baliga, Power Semiconductor Devices, pp. 376 et seq., (1996).
FIG. 7 shows pictorially the total drain-to-source resistance R.sub.DS in a planar DMOSFET. R.sub.channel is the channel resistance, R.sub.JFET is the resistance in the JFET region where the current is squeezed between the depletion regions surrounding the body-drain junctions, R.sub.spreading is the resistance in the region where the current is spreading out, R.sub.epi is the resistance in the remainder of the epi layer, and R.sub.substrate is the resistance of the substrate. As shown in FIG. 8, the total resistance of a trench-gated MOSFET is similar except that there is no R.sub.JFET. As a result, the trenchFET can be fabricated in higher cell densities than the planar DMOSFET. For example, the trenchFETs shown in FIGS. 9A and 9B, which contain a central deep diffusion as taught in the above-referenced U.S. Pat. No. 5,072,266 to Bulucea et al., can be fabricated to a density of about 12 million cells per square inch. If the technique taught in the above-referenced application Ser. No. 08/459,555 is used the density can be increased to about 32 million cells per square inch.
Getting a greater cell density alone is not enough. The critical parameter is the total channel width per unit area W/A (typically inverted as the packing coefficient A/W). Since the channel lies along the wall of the trench, the perimeter of each cell times the number of cells gives the total channel width. FIGS. 10A, 10B and 10C give the formulas for A/W for a trenchFET containing square, hexagonal and striped cells, respectively. Ysb is the length of a side of the cell and Yg is the length of the gate. In FIG. 10C, Z is the length of the stripe. A/W for the square and hexagonal cells is identical, and so long as the gate is smaller than the source-body region between the gates the square or hexagonal cell is better. Only if the regions between the gate are smaller than the gate is the striped configuration better.
For a trenchFET the normalized drain-to-source resistance R.sub.DS A is equal to the normalized channel resistance plus the normalized drain resistance (R.sub.JFET being zero). ##EQU2##
R.sub.Ch W can be expressed as: ##EQU3##
This essentially means that if the gate oxide is made thinner (.epsilon..sub.ox /x.sub.ox =C.sub.ox is greater) there is greater coupling to the channel and the channel resistance is lower. This incidentally has the complication of changing the threshold voltage unless the channel doping is adjusted in concert with oxide scaling.
Thus the channel resistance can be reduced by either thinning the gate oxide or improving A/W.
The remaining term is R.sub.D A which is expressed as: EQU R.sub.D A=.xi..multidot.x.sub.epi.multidot..rho..sub.epi +x.sub.sub.multidot..rho..sub.sub
where x.sub.epi and x.sub.sub represent the vertical distance through the epi layer and the substrate, respectively, and .rho..sub.epi and .rho..sub.sub represent the resistivity of the epi layer and substrate, respectively. .xi. is a correction factor at account for current spreading in some portion of the epi layer.
FIG. 11 is a graph showing the total normalized on-resistance as a function of the normalized gate oxide thickness for different levels of gate voltage in excess of the threshold voltage (V.sub.GS -Vt). The term (V.sub.GS -V.sub.t) is useful to eliminate the influence of process parameters on the threshold voltage when comparing the performance of various devices. This "overdrive" keeps the voltage beyond threshold constant so that other terms can be separated for analysis. In so doing the resistance in the epi layer and substrate can be separated from the channel term as X.sub.OX.fwdarw.0 and R.sub.Ch W.fwdarw.0. As the gate oxide thickness approaches zero the normalized resistance approaches a theoretical limit comprising the epi and substrate resistance which in this example is about 0.75 (i.e., 75%) of the total resistance of a reference device operated at a gate drive of 10 V above Vt, or around 12 V. Thus one can vary the gate oxide thickness and cell density to minimize the channel resistance but the resistance of the epi layer and substrate remain. For high voltage devices (e.g., 500 V) there is little reason to increase the cell density because so much of the resistance is attributable to the thick epi layer that is required to support a high breakdown voltage. Even for low voltage devices, eventually one runs into the limit represented by the resistance of the epi layer and substrate. In every case eventually the epi resistance becomes the dominant factor.
There is a great need for MOSFETs capable of handling voltages of 10 V up to 100 V or even 500 V and which have low on-resistances.
A different class of power devices is represented by the lateral MOSFET 120 shown in FIG. 12. MOSFET 120 is formed in a P-substrate or P-epi layer 121 and includes an N+ source 122, an N+ drain 123 and a P+ body contact region 124. A gate 125 is separated from a channel region by a gate oxide layer 126. The gate 125 can vary from 0.25 to 20-30 .mu.m in length, and the longer the channel the higher the on-resistance of the device. The on-resistance may be reduced by decreasing the gate oxide thickness, but eventually this is limited by the need to maintain a desired breakdown voltage. In many cases, to maintain the breakdown voltage at a desired level either the gate oxide has to be kept above a minimal thickness (otherwise the oxide between the N+ drain and the gate oxide will rupture) or a lightly doped drain extension has to be interposed between the gate and drain. Since these devices are commonly used in logic circuits, the higher on-resistance and lower transconductance and consequent slower speeds that result from these techniques to achieve a higher breakdown voltage present problems. So aside from thinning the oxide, decreasing resistance and improving transconductance must be accomplished in another way.
One solution to this problem, illustrated in FIG. 13A, is to form a thin silicon-germanium layer 127 immediately under the gate oxide layer 126, in the region of the channel. Layer 127 is a crystal that is a composite of silicon and germanium atoms wherein the germanium atoms might represent as much as 10% to 20% of the total number of atoms in the crystal lattice. Silicon and germanium are both Group IV elements and bond together covalently. For example, at a ratio of 10% one out of every ten atoms would be germanium and nine would be silicon. Layer 127 must be very thin--e.g., from 10 .ANG. to a few thousand .ANG. at most--and it is doped at a concentration which is much lower (e.g., 10.sup.13 or 10.sup.14 cm.sup.-3) than the concentration of a typical channel region (e.g., 10.sup.17 cm.sup.-3). FIG. 13B shows a graph of a the doping concentration and percentage of germanium as a function of the depth below the surface.
As a result of the difference in the energy band gap between silicon and silicon-germanium, carriers fall down an energy "hill" into the Si-Ge layer 127, which ideally is a lightly-doped layer. This is shown in FIG. 13C, which is a diagram showing the lowest conduction band energy E.sub.c in the germanium and silicon regions. Highly doped regions generally have low carrier mobility because the charge carriers are more likely to collide with each other. This produces scattering and energy in the form of heat. In the lightly doped Si-Ge layer, owing to the lower dopant concentration, the mobility of the carriers is much greater than it is in the silicon. Thus Si-Ge layer 127 functions as a tube or tunnel of very light dopant concentration which has a very high carrier mobility. The mobility of this layer is improved not only because of the presence of germanium (which has a higher mobility than silicon) but because the thin channel region is very lightly doped and therefore exhibits very little scattering due to interactions between the dopant (ions) and the channel carriers.
While numerous crystal defects are created by the mismatch between silicon and silicon-germanium, Si-Ge layer 127 is so thin that it is able to deform elastically to accommodate the more rigid underlying silicon. Si-Ge layer 127 must be very thin or the device will have a great deal of leakage and other undesirable properties. It should be noted that in the embodiment shown in FIGS. 13A-13C germanium is used to improve the channel mobility. This is an entirely different matter from the bulk drain resistance.
A thin Si-Ge layer has also been used to increase the carrier mobility in high electron mobility bipolar transistors (HEMTs), where it is used with a very narrow base region and polysilicon emitter. Again, the idea is to use the quantum mechanical effect of carriers falling into an energy well having a high mobility. FIG. 14 shows an HEMT 140 including an N-type polysilicon emitter 141, a P-type base 142, a Si-Ge layer 143 and an N-well 144 which serves as the collector of HEMT 140.
Neither of these applications addresses the problem of reducing the on-state resistance of a power MOSFET since, as described above, that resistance arises mainly in epitaxial or drift region of the device, not solely the channel. In the thin Si-Ge layer devices, moreover, the mobility in the Si-Ge layer is compared with the mobility in surface channel of silicon, which is already reduced to one-half or one-third of the mobility of bulk silicon. The significant improvement in mobility occurs not only because conduction is taking place in lightly doped regions but also because the concentration of the germanium can be tailored such that the carriers are "sucked" slightly below the surface. Therefore, scattering at the surface is avoided. In essence, the phenomenon is one of surface mobility and how to improve it by invoking partial bulk conduction, not properties in a bulk material. What is needed is a bulk material which contributes low resistance but supports a relatively high breakdown voltage. While wide bandgap semiconductors such as silicon carbide can offer such a benefit at high voltages and temperatures, devices using SiC are less efficient than even silicon at room temperature.